A technology disclosed in this specification relates to semiconductor devices, in particular to the structure of a high breakdown voltage MOS semiconductor device.
With increase in packing density of semiconductor integrated circuit devices in recent years, there is a growing demand for semiconductor integrated circuit devices including high breakdown voltage MOS elements, low breakdown voltage CMOS elements, and bipolar elements integrated on the same substrate. The high breakdown voltage MOS elements are required to have high breakdown voltage, low ON resistance, and low threshold voltage. The low ON resistance of the high breakdown voltage MOS element allows reduction in chip size. The low threshold voltage allows increase in margin for driving voltage and reduction in power consumption.
Conventionally, to achieve the high breakdown voltage MOS semiconductor devices, a technique of improving the breakdown voltage by forming an electric field relaxation layer in a drain region of the high breakdown voltage MOS element has been used. However, the electric field relaxation layer formed in the drain region acts as a resistance component when the transistor is operating. As a result, ON resistance per unit area of the element is increased. As such, there is a trade-off between the breakdown voltage and the ON resistance.
To cope with the trade-off problem, for example, Published Japanese Patent Application No. H09-260651 describes a technique of forming two offset regions as the electric field relaxation layer in a drain region of a high breakdown voltage MOS element for the purpose of achieving both improvement in breakdown voltage and reduction in ON resistance.
FIG. 11 is a cross-sectional view illustrating a conventional high breakdown voltage MOS transistor.
As shown in FIG. 11, the conventional high breakdown voltage MOS transistor includes: a p-type substrate 201; an n-type well region 202 formed in an upper portion of the substrate 201; an n-type base region 205 formed in an upper portion of the n-type well region 202; a p-type source region 203 formed in an upper portion of the n-type base region 205; a second p-type offset region 210 formed in an upper portion of the n-type well region 202; a first p-type offset region 206 formed in an upper portion of the second p-type offset region 210; a LOCOS oxide film 209 formed on the substrate 201; a gate oxide film 207 formed on the p-type source region 203; the n-type base region 205, the substrate 201 and the first p-type offset region 206 and connected to the LOCOS oxide film 209 at an end thereof; a gate electrode 208 formed on the gate oxide film 207; and a p-type drain region 204 formed in an upper portion of the first p-type offset region 206.
A surface impurity concentration of the first p-type offset region 206 is low, and an end thereof opposing the p-type source region 203 is closer to the p-type source region 203 than the second p-type offset region 210. The first p-type offset region 206 and the second p-type offset region 210 constitute a double offset region covering the bottom of the p-type drain region 204. The conventional high breakdown voltage MOS transistor is a lateral field-effect transistor configured as described above.
In this structure, part of the double offset region as a drain drift layer, i.e., part of the first p-type offset region 206 protruding toward the p-type source region 203, easily goes into a depletion state. On the other hand, part of the double offset region where the two offset regions overlap each other is less likely to go into the depletion state, and a reach through breakdown voltage is improved. In the double offset region, in particular when the first p-type offset region 206 which is lower in surface impurity concentration protrudes toward the p-type source region 203 more than the second p-type offset region 210 having higher surface impurity concentration, the first p-type offset region 206 is more likely to go into the depletion state, the second p-type offset region 210 having higher surface impurity concentration is less likely to go into the depletion state, and the reach through breakdown voltage is improved. Further, part of the gate oxide film 207 below part of the gate electrode 208 close to the p-type drain region 204 is thick. Therefore, an electric field below the thick part of the insulating film is relaxed, and the reach through breakdown voltage is easily enhanced.
As described above, in the conventional high breakdown voltage MOS transistor, provision of the first p-type offset region 206 and the second p-type offset region 210 allows relaxation of an electric field generated in the drain region, improvement in breakdown voltage, and reduction in resistance of a drift region. That is, both of improvement in breakdown voltage and reduction in ON resistance are achieved.